1. Field of the Invention
The present invention relates to high-density memory structures. In particular, the present invention relates to high-density memory structures formed by interconnected thin-film storage elements, such as thin-film storage transistors.
2. Discussion of the Related Art
In this disclosure, memory circuit structures are described. These structures may be fabricated on planar semiconductor substrates (e.g., silicon wafers) using conventional fabrication processes. To facilitate clarity in this description, the term “vertical” refers to the direction perpendicular to the surface of a semiconductor substrate, and the term “horizontal” refers to any direction that is parallel to the surface of that semiconductor substrate.
A number of high-density non-volatile memory structures, sometimes referred to as “three-dimensional vertical NAND strings,” are known in the prior art. Many of these high-density memory structures are formed using thin-film storage transistors formed out of deposited thin-films (e.g., polysilicon thin-films), and organized as arrays of “memory strings.” One type of memory strings is referred to as NAND memory strings or simply “NAND strings”. A NAND string consists of a number of series-connected storage transistors (“TFTs”). Reading or programming any of the series-connected TFTs requires activation of all series-connected TFTs in the NAND string. Under this NAND arrangement, the activated TFTs that are not read or programmed may experience undesirable program-disturb or read-disturb conditions. Further, TFTs formed out of polysilicon thin films have much lower channel mobility—and therefore higher resistivity—than conventional transistors formed in a single-crystal silicon substrate. The higher series resistance in the NAND string limits the number of TFTs in a string in practice to typically no more than 64 or 128 TFTs. The low read current that is required to be conducted through a long NAND string results in a long latency.
Another type of high density memory structures is referred to as the NOR memory strings or “NOR strings.” A NOR string includes a number of storage transistors each connected to a shared source region and a shared drain region. Thus, the transistors in a NOR string are connected in parallel, so that a read current in a NOR string is conducted over a much lesser resistance than the read current through a NAND string. At the present time, the present inventor is not aware of any NOR string in the prior art that is formed out of TFTs. To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated (i.e., “on” or conducting), all other storage transistors in the NOR string remain dormant (i.e., “off” or non-conducting). Consequently, a NOR string allows much faster sensing of the activated storage transistor to be read and avoids program-disturb or read-disturb conditions in the other storage transistors of the NOR string that are not read or programmed.
Three-dimensional memory structures are disclosed, for example, in U.S. Pat. No. 8,878,278 to Alsmeier et al. (“Alsmeier”), entitled “Compact Three Dimensional Vertical NAND and Method of Making Thereof,” filed on Jan. 30, 2013 and issued on Nov. 4, 2014. Alsmeier discloses various types of high-density NAND memory structures, such as “terabit cell array transistor” (TCAT) NAND arrays (FIG. 1A), “Pipe-Shaped Bit-Cost scalable” (P-BiCS) flash memory (FIG. 1B) and a “vertical NAND” memory string structure. Likewise, U.S. Pat. No. 7,005,350 to Walker et al. (“Walker I”), entitled “Method for Fabricating Programmable Memory Array Structures Incorporating Series—Connected Transistor Strings,” filed on Dec. 31, 2002 and issued on Feb. 28, 2006, also discloses a number of three-dimensional high-density NAND memory structures.
U.S. Pat. No. 7,612,411 to Walker (“Walker II”), entitled “Dual-Gate Device and Method” filed on Aug. 3, 2005 and issued on Nov. 3, 2009, discloses a “dual gate” memory structure, in which a common active region serves independently controlled storage elements in two NAND strings formed on opposite sides of the common active region.
U.S. Pat. No. 6,744,094 to Forbes (“Forbes”), entitled “Floating Gate Transistor with Horizontal Gate Layers Stacked Next to Vertical Body” filed on Aug. 24, 2001 and issued on Jun. 1, 2004, discloses memory structures having vertical body transistors with adjacent parallel horizontal gate layers.
U.S. Pat. No. 6,580,124 to Cleaves et al, entitled “Multigate Semiconductor Device with Vertical Channel Current and Method of Fabrication” filed on Aug. 14, 2000 and issued on Jun. 17, 2003, discloses a multibit memory transistor with two or four charge storage mediums formed along vertical surfaces of the transistor.
A three-dimensional memory structure, including horizontal NAND strings that are controlled by vertical polysilicon gates, is disclosed in the article “Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage” (“Kim”), by W. Kim at al., published in the 2009 Symposium on VLSI Tech. Dig. Of Technical Papers, pp 188-189. Horizontal 3D NAND strings with vertical poly gates. Another three-dimensional memory structure, also including horizontal NAND strings with vertical polysilicon gates, is disclosed in the article, “A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” by H. T. Lue et al., published in the 2010 Symposium on VLSI: Tech. Dig. Of Technical Papers, pp. 131-132.
In the memory structures discussed herein, stored information is represented by the stored electric charge, which may be introduced using any of a variety of techniques. For example, U.S. Pat. No. 5,768,192 to Eitan, entitled “Non-Volatile Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping,” filed on Jul. 23, 1996 and issued on Jun. 16, 1998, discloses NROM type memory transistor operation based on a “hot electron channel injection’ technique. Other techniques include Fowler-Nordheim tunneling used in TFT NAND strings, and direct tunneling, both of which are known to those of ordinary skill in the art.